Use the Merge tab to combine two or more circuits that are aligned in path but are separate circuits
because of different circuit IDs or conflicting parameters. A merge combines a single master circuit with one or more circuits.
The circuits that appear in the Merge tab are the circuits available for merging, which are all of the
circuits in the network except the following:
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Displays the name of the circuit. The circuit name can be manually assigned or automatically generated.
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Displays circuit types. Types are specific synchronous transport signal (STS circuit), virtual tributary (VT circuit), VTT (VT tunnel), IPT (IP tunnel), VAP (VT aggregation point), STS-V (STS VCAT circuit), and VT-V (VT VCAT circuit).
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Displays the circuit size, which depends on the source and destination card/port. VT circuits are 1.5. STS circuit sizes are STS-1, STS-3c (concatenated), STS-6c, STS-9c, STS-12c, STS-18c, STS-24c, STS-36c, STS-48c, or STS-192c.
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(ONS 15454) Displays the OCHNC wavelength for DWDM OCHNCs.
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Displays the circuit direction, either two-way or one-way.
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(ONS 15454) Displays the OCHNC direction, either East to West or West to East.
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Displays the circuit source in the format: node/slot/port “port name”/STS/VT. The port name appears in quotes. Node and slot is displayed; port “port name”/STS/VT is displayed, depending on the source card, circuit type, and name assigned to the port. If the circuit size is concatenated (3c, 6c, 12c, and so on.), STSs used in the circuit are displayed as ellipsis, for example, “S7..9,” (STSs 7, 8, and 9) or S10..12 (STSs 10, 11, and 12).
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If the port is on an ONS 15600 ASAP card, the port format is PIM-PPM-port_number. |
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If the port is on an ONS 15454 MRC-12 card, the port format is PPM-port_number. |
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Displays the circuit destination in the same format ( node/slot/port “port name”/STS/VT) as the circuit source.
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(ONS 15454 only) Displays the number of VLANs used by an Ethernet circuit.
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Displays the number of internode links that constitute the circuit. If you right-click the column, it displays a shortcut menu where you can choose to show or hide circuit span detail.
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Identifies if a port on the circuit is in loopback (LPBK).
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Merges the select circuits into the current circuit.
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Updates the Merge tab with current circuits that are available for merging.
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If checked, changes the circuit view in the graphic area to show circuit routing information including source slot, port, STS, and VT. The detailed view also shows working and protect circuit paths. If 802.17 RPR mode is enabled, the port displays as pRPR East or pRPR West.
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If checked, displays any VT tunnels that carry the VT circuit. If the circuit is not carried by a VT tunnel, no changes appear when the box is checked.
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If checked, hides the TXP and MXP connections where STS and VT circuits are routed, showing only the logical OC-N links. This check box is available only when circuits are routed on TXP or MXP cards provisioned in section or line mode.
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Displays context-sensitive help.
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